A Delta-Sigma Modulator (DSM) is a modulator that is arranged to, on receiving an input signal, output a modulated input signal having fewer bits (or a “lower resolution”) than the input signal. The term DSM is sometimes used interchangeably with the term Sigma-Delta Modulator (SDM). Hence, although only DSMs are referred to in the following, this term is intended to encompass both SDMs and DSMs.
The DSM is one of the most popular modulators for low to medium bandwidth applications due to its high resolution capability and noise shaping ability. It can be realised in either the analogue and or the digital domain. Analogue DSMs are mainly used for analogue to digital conversions. In contrast, Digital DSMs (DDSMs) are increasingly used in digital to analogue converters e.g. in an audio system, and in fractional-N frequency synthesisers e.g. in a phase locked loop (PLL).
FIG. 1 shows an example of an audio system comprising a DDSM. A digital codec 11 supplies a signal to DDSM 12. DDSM 12 outputs a modulated codec signal to Digital-to-Analogue-Converter (DAC) 13. The output of DAC 13 is buffered in buffer 14 before being filtered by filter 15 and driven by driver 16 through speaker 17. The DDSM 12 shapes the quantization noise to a high frequency region, where it is subsequently filtered out by the following filter 15 and the speaker 17. DDSMs are widely used in the output channel of an audio system in order to modulate a high resolution digital input (10-24 bits) data to low-resolution bit stream (1-5 bits).
FIG. 2 shows an example of a fractional-N synthesiser in a PLL that comprises a DDSM. A phase-frequency detector (PFD) 21 receives a reference signal fref and a feedback signal ffeed and compares fref with ffeed. Based on this comparison, the PFD 21 outputs a comparison signal to filter 22, which in turn outputs a filtered comparison signal to voltage controlled oscillator (VCO) 23. VCO 23 subsequently outputs a signal fout, which is input to further signal processing circuitry (not shown) and to fractional-N divider 24 in a feedback loop. Fractional-N divider 24 also receives a signal y[n] from DDSM 25. The factional-N divider 24 divides fout by (N+y[n]) and outputs signal ffeed. Signal ffeed is input to PFD 21 and DDSM 25. DDSM receives signal ffeed and signal x[n] and outputs signal y[n] to the fractional-N divider 24. Compared to an integer synthesizer, which divides by N instead of by N+y[n], a fractional-N synthesiser allows very narrow channel spacing relative to the output frequency and large bandwidth in the PLL relative to the channel spacing. DDSMs are used to create the fraction value in the feedback divider in order to mitigate the effect of fractional spurs and to decrease the base band fractional noise over those PPLs not having a DDSM.
FIG. 3 shows an example of the structure of a conventional DDSM. A summer 31 subtracts signal Y[n] from signal X[n] and outputs the result to filter 32. Filter 32 outputs signal U[n] to quantizer 33. Quantizer 33 outputs signal Y[n]. Signal Y[n] is passed to further signal processing circuitry (not shown) and to summer 31.
A DDSM is a finite state machine (FSM) and therefore, the number of available states is finite. If the input X[n], x[n] is constant (as is the case of the Fractional-N synthesisers mentioned above in relation to FIG. 2) or very low (such as when, in audio applications, the inputted signal represents silence), the DDSM can exhibit a trajectory that visits each state once before repeating. Therefore, DDSMs are prone to generating cycles that result in the presence of periodic components in the output spectrum.
When the DSM output bit stream Y[n], y[n] becomes cyclical and enters a repetitive pattern as mentioned above, a series of harmonics called “idle tones” or “spurs” are created at the output of the modulator. This reduces the performance of the system.
The presence of spurs in an output signal is disadvantageous in an audio system. For example, if the magnitude of the spurs in the audio range is bigger than the audible human threshold, they can become audible to a user. This may be irritating to a user.
The presence of spurs in an output signal is also disadvantageous in fractional-N synthesizers. The effect of spurs introduced by the DDSM into a PLL can be significant when combined with the effect of the nonlinearity of the phase detector. The spurs can break the transmit mask or desensitize the receiver in a radio system when the PLL is used to generate a carrier frequency.
It is therefore desirable to reduce or eliminate the DSM spurs in both PLL and Audio applications. This can be done by maximising the length of the cyclical repetitive pattern.
There are two classes of techniques for maximizing cycle lengths in DDSMs: “stochastic”; and “deterministic”.
The “stochastic” approach uses a dither signal to disrupt the periodic cycles, so increasing the cycle length. A dither signal may be a random sequence of noise. Adding a dither signal to a signal to be modulated introduces noise into the signal to be modulated. This makes it difficult to form periodic patterns, and thus spurs, in the modulated signal. Adding dither results in smoother noise-shaped spectra than in the case where no dither signal is added. An example showing the effect of adding a dither signal to a signal to be modulated is shown in FIGS. 4A and 4B.
In FIG. 4A, there is a sinusoidal signal and a superimposed truncated signal that is a digital representation of the sinusoidal signal. The truncated signal comprises the same quantization errors every period and so the cycle length is the period. Repeating the quantization error every period introduces spurs into the system.
In contrast, in FIG. 4B there is the same sinusoidal signal and a superimposed truncated signal formed from a digital representation of the sinusoidal signal and an additional dither signal. As the addition of the dither signal randomly introduces noise into the truncated signal, the truncated signal does not comprise the same quantization errors every period. Thus the cycle length in FIG. 4B is longer than a period and hence longer than the cycle length shown in FIG. 4A. Therefore, there are fewer spurs in this system than in the example shown in FIG. 4A.
The higher the dither amplitude, the more successfully idle-tones are removed. In order to remove the spurs completely, the power of the dither signal should be comparable with the power of the input signal to be modulated. However, the maximum power of the dither signal is limited by the maximum noise allowed in the circuit by the intended application (the noise specification of the circuit). Thus, for a given specification, spurs cannot be completely eliminated.
The “deterministic” approach uses an adapted modulator that is arranged to be unstable such that any repetitive pattern tends to be broken up. This can be done by configuring the filter 32 in the DDSM (see FIG. 3) such that the noise shaping zeros of the filter 32 are moved outside the unit circle in the z-domain. Deterministic systems are extremely sensitive to initial conditions and the speed in which they disrupt the cycle length is determined by how unstable the filter 32 is. Even though this technique increases the output noise, it does not completely eliminate tonality and repetitive patterns and hence spurs. In practice, deterministic approaches are avoided because the reliability of the approach is very sensitive to the initial conditions.
Some other techniques may also be used to increase the cycle length. For example, seeding, offsetting the input by 1-LSB for an increased word length and using prime modulus quantizers.
Among all the techniques, dithering has proved to be the most effective and simple way of suppressing the tonality of the DDSMs. However, in practical implementations, the noise specification of the circuits in which dithering is implemented means that spurs cannot be completely eliminated.
There is thus a need for a system that addresses these problems.